Negative Capacitance Clock Distribution

In this paper, we investigate the ever-increasing power issue that is poised to jeopardize performance and robustness of future low-power microprocessor design. We have observed a tremendous amount research in clock network design bolster energy-efficient computing, without, however, any substantial improvement overall performance. work, used emerging ferroelectric negative capacitance field-effect transistor (NCFET) reduce effective active elements, which enables clocking. According accurate HSPICE simulation, proposed NCFET-based clocking can save up 70 73 percent average compared industry standard schemes on industrial ISPD 2009 2010 benchmarks, respectively. addition, methodology uses 20 fewer buffers existing synthesized scheme exhibits 49 lower crosstalk-induced delay variation traditional CMOS-based